PCB-Level EMC, part III

Switch-mode-circuits & signallines

from 8:15am Welcome Coffee

8:45am Room open

9:00am Power-Integrity-measurements

  • Verification of the design
    • PDN-impedance-measurement
  • Verification of operation
    • Measuring ripple correctly

 X-Talk

  • Common-impedance-coupling
  • Field-coupling
  • Frequency response, estimates, measures

10:30am Coffee break

10:45am Signallines II

  • Filtering & termination
    • Limiting the bandwidth
    • Termination
  • Differential pairs
    • Theroetical vs. real properties
    • Proper design
    • Cable shields
    • Example: LVDS

12:30amLunch

01:30pmSwitch-mode circuits

  • EMC-issues
  • Fixes
    • Layout
    • Stackup
    • Circuit
  • Choice
    • Bricks vs. individual design

 Immunity: ESD & Burst

  • Disturbance properties
  • Coupling paths:
    • Test setup
    • EUT
  • Best practices:
    • Layout
    • Circuit

03:00pm Coffee break

03:15pm Connectors

  • EMC-impact
  • Grounding
  • Shields

~ 05:00pm Discussion